// `include "top_define.v"
module delete ( clk,
                rst_n,
                
                addr_b,
                data_b,
                wren_b,
                q_b, 
                
                time_now,
                studying,
                live_time_val,
                live_time_i
               );

//地址表中的数据{ 2'd0, sur_mac(48), sour_port(8), time_val, time_now(13) }
//mac表中写入的时间是当前时间-1
input clk;
input rst_n;

output[9 :0] addr_b;
output[71:0] data_b;
output wren_b;
input[71:0] q_b;

output reg[12:0] time_now;
input studying;

input live_time_val;
input [31:0] live_time_i;

reg[9:0] addr_b;
    
reg[71:0] data_b;
reg wren_b;

reg[9:0] addr_reg;            //9.1

reg[12:0] timer; //定时器，单位为秒
reg[19:0] count_1;
reg[9 :0] count_0;

reg[2:0] state;
reg[2:0] next_state;

reg [12:0] LIVE_TIME; //生存时间,5120秒

wire [12:0] live_time_temp;
assign live_time_temp = live_time_i[12:0];

//count1_up_limit * timer_up_limit  = 312500000(频率)
parameter COUNT1_UP_LIMIT = 19'd499999; //499999
parameter TIMER_UP_LIMIT  = 10'd624;  //624 生存时间，单位为秒        

always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
      count_0 <= 10'd0;
    else if(live_time_i[31]==1'b1)
      count_0 <= count_0;
    else if(count_0 == TIMER_UP_LIMIT)
      count_0 <= 10'd0;
    else 
      count_0 <= count_0 + 10'd1;
end
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
      count_1 <= 0;
    else if(live_time_i[31]==1'b1)
      count_1 <= count_1;
    else if(count_1 == COUNT1_UP_LIMIT && count_0 == TIMER_UP_LIMIT)
      count_1 <= 0;
    else if(count_0 == TIMER_UP_LIMIT)
      count_1 <= count_1 + 1;
    else 
      count_1 <= count_1;
end

always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
      timer <= 0;
    else if(live_time_i[31]==1'b1)
      timer <= timer;
    else if( count_1 == COUNT1_UP_LIMIT && count_0 == TIMER_UP_LIMIT && timer == LIVE_TIME)
      timer <= 0;
    else if( count_1 == COUNT1_UP_LIMIT && count_0 == TIMER_UP_LIMIT)
      timer <= timer + 13'd1;
    else 
      timer <= timer;
end

always @ (posedge clk or negedge rst_n)
  if(~rst_n)
    begin
      time_now <=  13'd0;
    end
  else
    begin
      if(timer==13'd0)
        time_now <=  LIVE_TIME;
      else
        time_now <=  timer - 13'd1;
    end
    
parameter  IDLE  = 3'b000,
           DATA  = 3'b001,
           DELETE= 3'b010,
           FINISH= 3'b100;
    
always @ (posedge clk or negedge rst_n)
  if(~rst_n)
    state <=  IDLE;
  else 
    state <=  next_state;
    
always @ (state or studying)
  case(state)
    IDLE:
      if(studying==1'b0)
        next_state = DATA;
      else
        next_state = IDLE;
    DATA:
      if(studying==1'b0)
        next_state = DELETE;
      else
        next_state = DATA;
    DELETE:
      if(studying==1'b0)
        next_state = FINISH;
      else
        next_state = DELETE;
    FINISH:
      next_state = IDLE;
    default:
      next_state = IDLE;
  endcase
           
always @ (posedge clk or negedge rst_n)
  if(~rst_n)
    begin
      addr_b <=  10'd0;
      data_b <=  72'd0;
      wren_b <=  1'b0;
      addr_reg <=  10'd0;
    end
    
  else
    begin
      case(state)
        IDLE:
          begin
            wren_b <=  1'b0;                                //开始读取数据
            data_b <=  72'd0;
            addr_b <=  addr_reg;
          end
          
        DATA:                                                   //等待一个周期
          begin
          end
         
        DELETE:
          begin
            if((q_b[12:0]==timer) && (q_b[13]==1'b1) && (LIVE_TIME != 13'd0))
              begin                                             //删除
                wren_b <=  1'b1;
                data_b <=  72'd0;
                addr_b <=  addr_reg;
              end
            else
              begin                                             //不删除
                wren_b <=  1'b0;
                data_b <=  72'd0;
                addr_b <=  addr_reg;
              end
          end
          
        FINISH:
          begin
            wren_b <=  1'b0;
            data_b <=  72'd0;
            addr_reg <=  addr_reg + 10'd1;
          end
		  default:
			begin
				wren_b <=  1'b0;    
				data_b <=  72'd0;
				addr_b <=  addr_reg;
      end
      endcase
    end

always @ (posedge clk or negedge rst_n)
   if(~rst_n)
      LIVE_TIME            <=         13'd4095;
   else if(live_time_val)
      LIVE_TIME            <=         live_time_temp;	
    
endmodule
